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Configuration Self-Scrubber for Xilinx Virtex-5QV FPGAs

Sandia National Laboratories

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Technology Marketing Summary

The Xilinx Virtex-5QV is a field programmable gate array (FPGA) designed for use in space applications. Despite radiation hardening of this particular FPGA, single-event upsets still occasionally corrupt the configuration memory of the device, requiring the use of a “scrubber” to correct these upset bits. Though scrubbing has historically required a separate external device, Sandia Labs developed a “self-scrubber” that scrubs the configuration memory of the same device in which it is implemented. This eliminates the need for a separate external device, significantly reducing the cost and complexity of programs that utilize Xilinx Virtex-5QV FPGAs.


The “self-scrubber” is a module written in VHDL that is intended to be integrated into a larger FPGA design. The self-scrubber module accesses the FPGA configuration memory through the internal ICAP configuration port and continually reads through the memory contents looking for errors. The self-scrubber corrects single-bit errors as they are discovered and is capable of reliably detecting double-bit errors in each frame. For frames with two or more bits in error, the errors are corrected by reloading the frame in error from an external memory. The “self-scrubber” is an extremely cost effective, power conservative, and reliable alternative to external scrubbing when mitigating errors in the configuration memory of the Virtex-5QV FPGA.


• Eliminates the use of expensive external devices to mitigate radiation damage

• Cost-efficient

• Easily programmable onto the device

• Continuous error correction in the configuration profile

Applications and Industries

• Space-based computing platforms that utilize Xilinx Virtex-5QV FPGA parts

Patents and Patent Applications
ID Number
Title and Abstract
Primary Lab
Patent 9,274,895
Processing device with self-scrubbing logic
An apparatus includes a processing unit including a configuration memory and self-scrubber logic coupled to read the configuration memory to detect compromised data stored in the configuration memory. The apparatus also includes a watchdog unit external to the processing unit and coupled to the self-scrubber logic to detect a failure in the self-scrubber logic. The watchdog unit is coupled to the processing unit to selectively reset the processing unit in response to detecting the failure in the self-scrubber logic. The apparatus also includes an external memory external to the processing unit and coupled to send configuration data to the configuration memory in response to a data feed signal outputted by the self-scrubber logic.
Sandia National Laboratories 03/01/2016
Technology Status
Technology IDDevelopment StageAvailabilityPublishedLast Updated
SD#12505Prototype - Sandia estimates this technology at a Technology Readiness Level 5. Components are integrated with reasonably realistic supporting elements so it can be tested in a simulated environment.Available08/25/201608/25/2016

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