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Memory hierarchy using row-based compression

United States Patent

October 25, 2016
View the Complete Patent at the US Patent & Trademark Office
Lawrence Livermore National Laboratory - Visit the Industrial Partnerships Office Website
A system includes a first memory and a device coupleable to the first memory. The device includes a second memory to cache data from the first memory. The second memory includes a plurality of rows, each row including a corresponding set of compressed data blocks of non-uniform sizes and a corresponding set of tag blocks. Each tag block represents a corresponding compressed data block of the row. The device further includes decompression logic to decompress data blocks accessed from the second memory. The device further includes compression logic to compress data blocks to be stored in the second memory.
Loh; Gabriel H. (Bellevue, WA), O'Connor; James M. (Austin, TX)
Advanced Micro Devices, Inc. (Sunnyvale, CA)
13/ 939,377
July 11, 2013
GOVERNMENT LICENSE RIGHTS This invention was made with government support under Prime Contract Number DE-AC52-07NA27344, Subcontract Number B600716 awarded by the Department of Energy (DOE). The Government has certain rights in this invention.