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Single event upset protection circuit and method

United States Patent

March 22, 2016
View the Complete Patent at the US Patent & Trademark Office
Sandia National Laboratories - Visit the Intellectual Property Management and Licensing Website
An SEU protection circuit comprises first and second storage means for receiving primary and redundant versions, respectively, of an n-bit wide data value that is to be corrected in case of an SEU occurrence; the correction circuit requires that the data value be a 1-hot encoded value. A parity engine performs a parity operation on the n bits of the primary data value. A multiplexer receives the primary and redundant data values and the parity engine output at respective inputs, and is arranged to pass the primary data value to an output when the parity engine output indicates `odd` parity, and to pass the redundant data value to the output when the parity engine output indicates `even` parity. The primary and redundant data values are suitably state variables, and the parity engine is preferably an n-bit wide XOR or XNOR gate.
Wallner; John (Camarillo, CA), Gorder; Michael (Westlake Village, CA)
14/ 290,648
May 29, 2014
GOVERNMENT RIGHTS This invention was made with Government support under US Department of Energy Contract No. DE-AC04-94AL85000. The Government has certain rights in this invention.