Skip to Content
Find More Like This
Return to Search

Detecting and correcting hard errors in a memory array

United States Patent

November 17, 2015
View the Complete Patent at the US Patent & Trademark Office
Lawrence Livermore National Laboratory - Visit the Industrial Partnerships Office Website
Hard errors in the memory array can be detected and corrected in real-time using reusable entries in an error status buffer. Data may be rewritten to a portion of a memory array and a register in response to a first error in data read from the portion of the memory array. The rewritten data may then be written from the register to an entry of an error status buffer in response to the rewritten data read from the register differing from the rewritten data read from the portion of the memory array.
Kalamatianos; John (Arlington, MA), John; Johnsy Kanjirapallil (Acton, MA), Gelinas; Robert (Needham, MA), Sridharan; Vilas K. (Brookline, MA), Nevius; Phillip E. (Arlington, MA)
Advanced Micro Devices, Inc. (Sunnyvale, CA)
14/ 048,830
October 8, 2013
GOVERNMENT LICENSE RIGHTS This invention was made with government support under Prime Contract Number DE-AC52-07NA27344, Subcontract Number B600716 awarded by the Department of Energy (DOE). The Government has certain rights in this invention.