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Three-dimensional stacked structured ASIC devices and methods of fabrication thereof

United States Patent

November 17, 2015
View the Complete Patent at the US Patent & Trademark Office
Sandia National Laboratories - Visit the Intellectual Property Management and Licensing Website
A 3D stacked sASIC is provided that includes a plurality of 2D reconfigurable structured structured ASIC (sASIC) levels interconnected through hard-wired arrays of 3D vias. The 2D sASIC levels may contain logic, memory, analog functions, and device input/output pad circuitry. During fabrication, these 2D sASIC levels are stacked on top of each other and fused together with 3D metal vias. Such 3D vias may be fabricated as through-silicon vias (TSVs). They may connect to the back-side of the 2D sASIC level, or they may be connected to top metal pads on the front-side of the 2D sASIC level.
Shinde; Subhash L. (Albuquerque, NM), Teifel; John (Albuquerque, NM), Flores; Richard S. (Albuquerque, NM), Jarecki, Jr.; Robert L. (Albuquerque, NM), Bauer; Todd (Albuquerque, NM)
Sandia Corporation (Albuquerque, NM)
14/ 283,101
May 20, 2014
STATEMENT OF GOVERNMENT INTEREST This invention was developed under Contract DE-AC04-94AL85000 between Sandia Corporation and the U.S. Department of Energy. The U.S. Government has certain rights in this invention.