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Testing and operating a multiprocessor chip with processor redundancy

United States Patent

October 21, 2014
View the Complete Patent at the US Patent & Trademark Office
A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.
Bellofatto; Ralph E. (Ridgefield, CT), Douskey; Steven M. (Rochester, MN), Haring; Rudolf A. (Cortlandt Manor, NY), McManus; Moyra K. (Peekskill, NY), Ohmacht; Martin (Yorktown Heights, NY), Schmunkamp; Dietmar (Schoenaich, DE), Sugavanam; Krishnan (Elmsford, NY), Weatherford; Bryan J. (Essex Junction, VT)
International Business Machines Corporation (Armonk, NY)
13/ 196,459
August 2, 2011
GOVERNMENT CONTRACT This invention was made with Government support under Contract No. B554331 awarded by Department of Energy. The Government has certain rights in this invention.