Skip to Content
Find More Like This
Return to Search

DMA shared byte counters in a parallel computer

United States Patent

April 6, 2010
View the Complete Patent at the US Patent & Trademark Office
A parallel computer system is constructed as a network of interconnected compute nodes. Each of the compute nodes includes at least one processor, a memory and a DMA engine. The DMA engine includes a processor interface for interfacing with the at least one processor, DMA logic, a memory interface for interfacing with the memory, a DMA network interface for interfacing with the network, injection and reception byte counters, injection and reception FIFO metadata, and status registers and control registers. The injection FIFOs maintain memory locations of the injection FIFO metadata memory locations including its current head and tail, and the reception FIFOs maintain the reception FIFO metadata memory locations including its current head and tail. The injection byte counters and reception byte counters may be shared between messages.
Chen; Dong (Croton on Hudson, NY), Gara; Alan G. (Mount Kisco, NY), Heidelberger; Philip (Cortlandt Manor, NY), Vranas; Pavlos (Danville, CA)
International Business Machines Corporation (Armonk, NY)
11/ 768,781
June 26, 2007
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT The U.S. Government has a paid-up license in this invention and the right in limited circumstances to require the patent owner to license others on reasonable terms as provided for by the terns of Contract. No. B554331 awarded by the Department of Energy.