Skip to Content
Find More Like This
Return to Search

3-D readout-electronics packaging for high-bandwidth massively paralleled imager

United States Patent

December 18, 2007
View the Complete Patent at the US Patent & Trademark Office
Los Alamos National Laboratory - Visit the Technology Transfer Division Website
Dense, massively parallel signal processing electronics are co-packaged behind associated sensor pixels. Microchips containing a linear or bilinear arrangement of photo-sensors, together with associated complex electronics, are integrated into a simple 3-D structure (a "mirror cube"). An array of photo-sensitive cells are disposed on a stacked CMOS chip's surface at a angle from light reflecting mirror surfaces formed on a neighboring CMOS chip surface. Image processing electronics are held within the stacked CMOS chip layers. Electrical connections couple each of said stacked CMOS chip layers and a distribution grid, the connections for distributing power and signals to components associated with each stacked CSMO chip layer.
Kwiatkowski; Kris (Los Alamos, NM), Lyke; James (Albuquerque, NM)
U.S. Department of Energy (Washington, DC)
10/ 901,309
July 26, 2004
STATEMENT OF GOVERNMENT RIGHTS The United States Government has rights in this invention pursuant to Contract No. W-7405-ENG-36 between the United States Department of Energy and the University of California for the operation of the Los Alamos National Laboratory.