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Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications

United States Patent

July 31, 2001
View the Complete Patent at the US Patent & Trademark Office
Sandia National Laboratories - Visit the Intellectual Property Management and Licensing Website
A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.
Schwank; James R. (Albuquerque, NM), Shaneyfelt; Marty R. (Albuquerque, NM), Draper; Bruce L. (Albuquerque, NM), Dodd; Paul E. (Tijeras, NM)
Sandia Corporation (Albuquerque, NM)
09/ 270,374
March 16, 1999
GOVERNMENT RIGHTS This invention was made with Government support under Contract No. DE-AC04-94AL85000 awarded by the U.S. Department of Energy. The Government has certain rights in the invention.