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Semiconductor P-I-N detector

United States Patent

July 3, 2001
View the Complete Patent at the US Patent & Trademark Office
A semiconductor P-I-N detector including an intrinsic wafer, a P-doped layer, an N-doped layer, and a boundary layer for reducing the diffusion of dopants into the intrinsic wafer. The boundary layer is positioned between one of the doped regions and the intrinsic wafer. The intrinsic wafer can be composed of CdZnTe or CdTe, the P-doped layer can be composed of ZnTe doped with copper, and the N-doped layer can be composed of CdS doped with indium. The boundary layers is formed of an undoped semiconductor material. The boundary layer can be deposited onto the underlying intrinsic wafer. The doped regions are then typically formed by a deposition process or by doping a section of the deposited boundary layer.
Sudharsanan; Rengarajan (Nashua, NH), Karam; Nasser H. (Lexington, MA)
08/ 949,015
October 10, 1997
This invention was made with Government's support under Grant No. DE-FG02-94ER81869 awarded by The Department of Energy. The Government has certain rights in this invention.