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VHDL technology library method for efficient customization of chip gate delays

United States Patent Application

View the Complete Application at the US Patent & Trademark Office
Lawrence Livermore National Laboratory - Visit the Industrial Partnerships Office Website
A method and system update a VHDL technology library (306) to incorporate correlated delay values by reading the VHDL technology library (306), inserting a tpd_super_rise_time generic declaration and a tpd_super_fall_time generic declaration for every VHDL gate model in the VHDL technology library (306), initializing other generic variables in every VHDL gate model in the VHDL technology library to an equation representing a correlation policy; and outputting an updated VHDL technology library. Then, the method and system bind correlated delay constants in a 3-dimensional variable data array structure to a VHDL technology library (306) using a VHDL package embedded with the correlation delay data.
Rich, Marvin J. (Poughkeepsie, NY), Misra, Ashutosh (Bangalore, IN)
10/ 038,689
January 2, 2002
[0002] This invention was made with government support under subcontract B338307 under prime contract W-7405-ENG-48 awarded by the Department of Energy. The Government has certain rights in this invention.