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Hybrid Group IV/III-V Semiconductor Structures

United States Patent Application

View the Complete Application at the US Patent & Trademark Office
Described herein are semiconductor structures comprising (i) a Si substrate; (ii) a buffer region formed directly over the Si substrate, wherein the buffer region comprises (a) a Ge layer having a threading dislocation density below about 10.sup.5 cm.sup.-2; or (b) a Ge.sub.1-xSn.sub.x layer formed directly over the Si substrate and a Ge.sub.1-x-ySi.sub.xSn.sub.y layer formed over the Ge.sub.1-xSn.sub.x layer; and (iii) a plurality of III-V active blocks formed over the buffer region, wherein the first III-V active block formed over the buffer region is lattice matched or pseudomorphically strained to the buffer region. Further, methods for forming the semiconductor structures are provided and novel Ge.sub.1-x-ySi.sub.xSn.sub.y, alloys are provided that are lattice matched or pseudomorphically strained to Ge and have tunable band gaps ranging from about 0.80 eV to about 1.4O eV.
Kouvetakis, John (Mesa, AZ), Menendez, Jose (Tempe, AZ)
Arizona Board of Regents, a body corporate acting for and on behalf of Arizona State University (Scottsdale AZ)
13/ 062,304
September 16, 2009
STATEMENT OF GOVERNMENT FUNDING [0002] The invention described herein was made in part with government support under grant number FA9550-60-01-0442, awarded by the US-AFOSR and the Department of Energy under Grant No. DE-FG36-08GO1800. The United States Government has certain rights in the invention.