Skip to Content
Find More Like This
Return to Search

Techniques for Growth of Lattice-Matched Semiconductor Layers

For the fabrication of multi-junction solar cells, light emitting diodes, and high speed transistors

National Renewable Energy Laboratory

Contact NREL About This Technology


Technology Marketing Summary

There are many potential applications for high-performance devices fabricated using III-V materials, including high efficiency solar cells, solid-state lighting, and high-speed transistors. In each case, the specific device designs rely on combinations of various materials where the lattice mismatch between the different materials can introduce problems for device performance and the deposition processes can be cost-prohibitive. With each of these markets approaching multi-billion dollars each year, there exists a clear need for a technology solution to produce these devices with higher performance faster and cheaper than the existing state-of-the-art.

Description

Our existing portfolio of lattice matching technologies aims to find solutions by matching the lattice structures of the various materials so that one may be grown on another to provide the desired device properties and performance. In particular, this portfolio allows for the use of low-cost and scalable processing methods and substrates for growing III-V materials and the reuse of those substrates to dramatically reduce production costs. In addition, the portfolio provides various schemes for growing certain types of III-V material combinations to provide desired bandgap energies capable of absorbing a certain range of energy for PV applications, or for emitting certain wavelengths of light in solid-state lighting applications, or for fabricating high speed or high power transistor devices.

As one example, the technologies can be used to grow lattice-matched InGaN alloys for fabrication of a green LED. InGaN alloys are of great interest for the manufacture of light emitting diodes and lasers for use in solid-state lighting applications. However, there is presently a difficulty in creating devices that emit light efficiently at wavelengths between 500 nm and 600 nm, known as the “green gap.” One possible cause of this is that material quality in this region is degraded due to a tendency toward phase separation of the InGaN. The present invention provides a solution by growing lattice-matched InGaN alloys in which phase separation can be suppressed.

Another application of the invention is the fabrication of high electron mobility III-V heterostructures suitable for high-speed transistors that can leverage existing semiconductor chip manufacturing infrastructure and processes.

Benefits
  • Eliminates phase separation and piezoelectric polarization effects
  • Removes need to grow graded lattice parameter buffer layers
  • Lowers cost by use of cheap, large area substrates
  • Enables use of more optimum bandgap combinations for multi-junction solar cells
  • Can make use of existing semiconductor chip manufacturing know-how
Applications and Industries
  • Solid-state lighting
  • High efficiency multi-junction solar cells
  • Power and high speed electronics
Patents and Patent Applications
ID Number
Title and Abstract
Primary Lab
Date
Application 20110049520
Application
20110049520
LATTICE MATCHED CRYSTALLINE SUBSTRATES FOR CUBIC NITRIDE SEMICONDUCTOR GR
Disclosed embodiments include methods of fabricating a semiconductor layer or device and devices fabricated thereby. The methods include, but are not limited to, providing a substrate having a cubic crystalline surface with a known lattice parameter and growing a cubic crystalline group III-nitride alloy layer on the cubic crystalline substrate by coincident site lattice matched epitaxy. The cubic crystalline group III-nitride alloy may be prepared to have a lattice parameter (a') that is related to the lattice parameter of the substrate (a). The group III-nitride alloy may be a cubic crystalline In.sub.xGa.sub.yAl.sub.1-x-yN alloy. The lattice parameter of the In.sub.xGa.sub.yAl.sub.1-x-yN or other group III-nitride alloy may be related to the substrate lattice parameter by (a')= 2(a) or (a')=(a)/ 2. The semiconductor alloy may be prepared to have a selected band gap.
National Renewable Energy Laboratory 08/31/2009
Filed
Patent 8,507,365
Patent
8,507,365
Growth of coincident site lattice matched semiconductor layers and devices on crystalline substrates
Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a substrate having a crystalline surface with a known lattice parameter (a). The method further includes growing a crystalline semiconductor layer on the crystalline substrate surface by coincident site lattice matched epitaxy, without any buffer layer between the crystalline semiconductor layer and the crystalline surface of the substrate. The crystalline semiconductor layer will be prepared to have a lattice parameter (a') that is related to the substrate lattice parameter (a). The lattice parameter (a') maybe related to the lattice parameter (a) by a scaling factor derived from a geometric relationship between the respective crystal lattices.
National Renewable Energy Laboratory 08/13/2013
Issued
Patent 8,575,471
Patent
8,575,471
Lattice matched semiconductor growth on crystalline metallic substrates
Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a metal or metal alloy substrate having a crystalline surface with a known lattice parameter (a). The methods further include growing a crystalline semiconductor alloy layer on the crystalline substrate surface by coincident site lattice matched epitaxy. The semiconductor layer may be grown without any buffer layer between the alloy and the crystalline surface of the substrate. The semiconductor alloy may be prepared to have a lattice parameter (a') that is related to the lattice parameter (a). The semiconductor alloy may further be prepared to have a selected band gap.
11/05/2013
Issued
Application 20130256751
Application
20130256751
METHODS OF PRODUCING FREE-STANDING SEMICONDUCTORS USING SACRIFICIAL BUFFER LAYERS AND RECYCLABLE SUBSTRATES
A method of producing semiconductor materials and devices that incorporate the semiconductor materials are provided. In particular, a method is provided of producing a semiconductor material, such as a III-V semiconductor, on a spinel substrate using a sacrificial buffer layer, and devices such as photovoltaic cells that incorporate the semiconductor materials. The sacrificial buffer material and semiconductor materials may be deposited using lattice-matching epitaxy or coincident site lattice-matching epitaxy, resulting in a close degree of lattice matching between the substrate material and deposited material for a wide variety of material compositions. The sacrificial buffer layer may be dissolved using an epitaxial liftoff technique in order to separate the semiconductor device from the spinel substrate, and the spinel substrate may be reused in the subsequent fabrication of other semiconductor devices. The low-defect density semiconductor materials produced using this method result in the enhanced performance of the semiconductor devices that incorporate the semiconductor materials.
National Renewable Energy Laboratory 12/01/2010
Filed
Application 20130333751
Application
20130333751
COINCIDENT SITE LATTICE-MATCHED GROWTH OF SEMICONDUCTORS ON SUSTRATES USING COMPLIANT BUFFER LAYERS
A method of producing semiconductor materials and devices that incorporate the semiconductor materials are provided. In particular, a method is provided of producing a semiconductor material, such as a III-V semiconductor, on a silicon substrate using a compliant buffer layer, and devices such as photovoltaic cells that incorporate the semiconductor materials. The compliant buffer material and semiconductor materials may be deposited using coincident site lattice-matching epitaxy, resulting in a close degree of lattice matching between the substrate material and deposited material for a wide variety of material compositions. The coincident site lattice matching epitaxial process, as well as the use of a ductile buffer material, reduce the internal stresses and associated crystal defects within the deposited semiconductor materials fabricated using the disclosed method. As a result, the semiconductor devices provided herein possess enhanced performance characteristics due to a relatively low density of crystal defects.
National Renewable Energy Laboratory 12/01/2010
Filed
Technology Status
Technology IDDevelopment StageAvailabilityPublishedLast Updated
08-34; 08-40; 08-60; 10-37; 10-44 Prototype - The technology has been reduced to practice and prototype devices are being created to demonstrate the potential applications.Available - Please contact the NREL Commercialization and Technology Transfer Office for information concerning a license to use the technology, or a partnership to further develop it. 08/13/201012/27/2013

Contact NREL About This Technology

To: Bill Hadley<Bill.Hadley@nrel.gov>