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Jitter compensation circuit

United States Patent

*** EXPIRED ***
September 9, 1997
View the Complete Patent at the US Patent & Trademark Office
Lawrence Livermore National Laboratory - Visit the Industrial Partnerships Office Website
The instantaneous signal on a charging capacitor is sampled and the charge voltage on capacitor C.sub.o is captured just prior to its discharge into the first stage of magnetic modulator. The captured signal is applied to an averaging circuit with a long time constant and to the positive input terminal of a differential amplifier. The averaged V.sub. co signal is split between a gain stage (G=0.975) and a feedback stage that determines the slope of the voltage ramp applied to the high speed comparator. The 97.5% portion of the averaged signal is applied to the negative input of a differential amplifier gain stage (G=10). The differential amplifier produces an error signal by subtracting 97.5% of the averaged signal from the instantaneous value of sampled signal and multiplying the difference by ten. The resulting error signal is applied to the positive input of a high speed comparator. The error signal is then compared to a voltage ramp that is proportional to the averaged values squared divided by the total volt-second product of the magnetic compression circuit.
Sullivan; James S. (Livermore, CA), Ball; Don G. (Livermore, CA)
The United States of America as represented by the United States (Washington, DC)
08/ 340,408
November 15, 1994
GOVERNMENT RIGHTS The United States Government has rights in this invention pursuant to Contract No. W-7405-ENG-48 between the United States Department of Energy and the University of California.