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Repairable chip bonding/interconnect process

United States Patent

5,653,019
August 5, 1997
View the Complete Patent at the US Patent & Trademark Office
Lawrence Livermore National Laboratory - Visit the Industrial Partnerships Office Website
A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder.
Bernhardt; Anthony F. (Berkeley, CA), Contolini; Robert J. (Livermore, CA), Malba; Vincent (Livermore, CA), Riddle; Robert A. (Tracy, CA)
Regents of the University of California (Oakland, CA)
08/ 522,471
August 31, 1995
The United States Government has rights in this invention pursuant to Contract No. W-7405-ENG-48 between the United States Department of Energy and the University of California for the operation of Lawrence Livermore National Laboratory.