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Gated integrator with signal baseline subtraction

United States Patent

5,585,756
December 17, 1996
View the Complete Patent at the US Patent & Trademark Office
Argonne National Laboratory - Visit the Technology Development and Commercialization Website
An ultrafast, high precision gated integrator includes an opamp having differential inputs. A signal to be integrated is applied to one of the differential inputs through a first input network, and a signal indicative of the DC offset component of the signal to be integrated is applied to the other of the differential inputs through a second input network. A pair of electronic switches in the first and second input networks define an integrating period when they are closed. The first and second input networks are substantially symmetrically constructed of matched components so that error components introduced by the electronic switches appear symmetrically in both input circuits and, hence, are nullified by the common mode rejection of the integrating opamp. The signal indicative of the DC offset component is provided by a sample and hold circuit actuated as the integrating period begins. The symmetrical configuration of the integrating circuit improves accuracy and speed by balancing out common mode errors, by permitting the use of high speed switching elements and high speed opamps and by permitting the use of a small integrating time constant. The sample and hold circuit substantially eliminates the error caused by the input signal baseline offset during a single integrating window.
Wang; Xucheng (Lisle, IL)
University of Chicago (Chicago, IL)
08/ 394,958
February 27, 1995
CONTRACTUAL ORIGIN OF THE INVENTION The United States Government has rights in this invention pursuant to Contract No. W-31-109-ENG-38, between the U.S. Department of Energy and The University of Chicago, representing Argonne National Laboratory.