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IC layout adjustment method and tool for improving dielectric reliability at interconnects

United States Patent

9,922,161
March 20, 2018
View the Complete Patent at the US Patent & Trademark Office
Sandia National Laboratories - Visit the Intellectual Property Management and Licensing Website
Method for adjusting a layout used in making an integrated circuit includes one or more interconnects in the layout that are susceptible to dielectric breakdown are selected. One or more selected interconnects are adjusted to increase via to wire spacing with respect to at least one via and one wire of the one or more selected interconnects. Preferably, the selecting analyzes signal patterns of interconnects, and estimates the stress ratio based on state probability of routed signal nets in the layout. An annotated layout is provided that describes distances by which one or more via or wire segment edges are to be shifted. Adjustments can include thinning and shifting of wire segments, and rotation of vias.
Kahng; Andrew B. (Del Mar, CA), Chan; Tuck Boon (La Jolla, CA)
The Regents of the University of California (Oakland, CA)
14/ 767,458
February 20, 2014
The invention was made with government support under 1187086 (DE-AC04-94AL8500) awarded by the Department of Energy. The Government has certain rights in the invention.