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Low power adaptive synchronizer

United States Patent

February 20, 2018
View the Complete Patent at the US Patent & Trademark Office
Lawrence Livermore National Laboratory - Visit the Industrial Partnerships Office Website
A circuit adapts to the occurrence of metastable states. The circuit inhibits passing of the metastable state to circuits that follow, by clock gating the output stage. In order to determine whether or not to gate the clock of the output stage, two detect circuits may be used. One circuit detects metastability and another circuit detects metastability resolved to a wrong logic level. The results from one or both detector circuits are used to gate the next clock cycle if needed, waiting for the metastable situation to be resolved.
Sadowski; Greg (Boxborough, MA)
Advanced Micro Devices, Inc. (Sunnyvale, CA)
15/ 239,217
August 17, 2016
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT This invention was made with Government support under Prime Contract Number DE-AC52-07NA27344, Subcontract No. B609201, awarded by the Department of Energy. The Government has certain rights in the invention.