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Scalable polylithic on-package integratable apparatus and method

United States Patent

December 5, 2017
View the Complete Patent at the US Patent & Trademark Office
Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.
Khare; Surhud (Bangalore, IN), Somasekhar; Dinesh (Portland, OR), Borkar; Shekhar Y. (Beaverton, OR)
Intel Corporation (Santa Clara, CA)
14/ 967,231
December 11, 2015
GOVERNMENT LICENSE RIGHTS This invention was made with Government support under contract number B608115 awarded by the Department of Energy. The Government has certain rights in this invention.