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Accessing memory

United States Patent

September 26, 2017
View the Complete Patent at the US Patent & Trademark Office
A disclosed example method involves performing simultaneous data accesses on at least first and second independently selectable logical sub-ranks to access first data via a wide internal data bus in a memory device. The memory device includes a translation buffer chip, memory chips in independently selectable logical sub-ranks, a narrow external data bus to connect the translation buffer chip to a memory controller, and the wide internal data bus between the translation buffer chip and the memory chips. A data access is performed on only the first independently selectable logical sub-rank to access second data via the wide internal data bus. The example method also involves locating a first portion of the first data, a second portion of the first data, and the second data on the narrow external data bus during separate data transfers.
Yoon; Doe Hyun (San Jose, CA), Muralimanohar; Naveen (Santa Clara, CA), Chang; Jichuan (Sunnyvale, CA), Ranganthan; Parthasarathy (San Jose, CA)
Hewlett Packard Enterprise Development LP (Houston, TX)
14/ 405,904
June 8, 2012
STATEMENT OF GOVERNMENT INTEREST This invention has been made with government support under Contract No. DE-SC0005026, awarded by The Department of Energy. The government has certain rights in the invention.