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Multiple core computer processor with globally-accessible local memories

United States Patent

September 20, 2016
View the Complete Patent at the US Patent & Trademark Office
Lawrence Berkeley National Laboratory - Visit the Technology Transfer and Intellectual Property Management Department Website
A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores.
Shalf; John (Oakland, CA), Donofrio; David (San Francisco, CA), Oliker; Leonid (San Francisco, CA)
The Regents of the University of California (Oakland, CA)
14/ 354,257
October 26, 2012
STATEMENT OF GOVERNMENT SUPPORT This invention was made with government support under Contract No. DE-AC02-05CH11231 awarded by the U.S. Department of Energy. The government has certain rights in this invention.