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Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

United States Patent

March 15, 2016
View the Complete Patent at the US Patent & Trademark Office
A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.
Asaad; Sameh W. (Briarcliff Manor, NY), Kapur; Mohit (Sleepy Hollow, NY)
International Business Machines Corporation (Armonk, NY)
13/ 435,707
March 30, 2012
STATEMENT OF GOVERNMENT INTEREST This invention was made with Government support under Contract No.: B554331 awarded by the Department of Energy (DOE). The Government has certain rights in this invention.