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Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator

United States Patent

January 5, 2016
View the Complete Patent at the US Patent & Trademark Office
A method, system and computer program product are disclosed for generating clock signals for a cycle accurate FPGA based hardware accelerator used to simulate operations of a device-under-test (DUT). In one embodiment, the DUT includes multiple device clocks generating multiple device clock signals at multiple frequencies and at a defined frequency ratio; and the FPG hardware accelerator includes multiple accelerator clocks generating multiple accelerator clock signals to operate the FPGA hardware accelerator to simulate the operations of the DUT. In one embodiment, operations of the DUT are mapped to the FPGA hardware accelerator, and the accelerator clock signals are generated at multiple frequencies and at the defined frequency ratio of the frequencies of the multiple device clocks, to maintain cycle accuracy between the DUT and the FPGA hardware accelerator. In an embodiment, the FPGA hardware accelerator may be used to control the frequencies of the multiple device clocks.
Asaad; Sameth W. (Briarcliff Manor, NY), Kapur; Mohit (Sleepy Hollow, NY)
International Business Machines Corporation (Armonk, NY)
13/ 435,614
March 30, 2012
STATEMENT OF GOVERNMENT INTEREST This invention was made with Government support under Contract No.: B554331 awarded by Department of Energy (DOE). The Government has certain rights in this invention.