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High voltage MOSFET devices and methods of making the devices

United States Patent

December 15, 2015
View the Complete Patent at the US Patent & Trademark Office
A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.
Banerjee; Sujit (San Jose, CA), Matocha; Kevin (Round Rock, TX), Chatty; Kiran (Round Rock, TX)
14/ 456,110
August 11, 2014
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT This invention was made with government support under Grant No. DE-AR0000442 awarded by the Department of Energy. The government has certain rights in the invention.