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Semiconductive micro- and nano-wire array manufacturing

United States Patent

June 2, 2015
View the Complete Patent at the US Patent & Trademark Office
The disclosure provides methods of manufacturing semiconductive structures using stamping and VLS techniques.
Warren; Emily L. (Pasadena, CA), Audesirk; Heather A. (Los Angeles, CA), Lewis; Nathan S. (La Canada Flintridge, CA)
California Institute of Technology (Pasadena, CA)
13/ 972,809
August 21, 2013
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH This invention was made with government support under grant numbers DE-FG02-05ER15754 awarded by the U.S. Department of Energy. The government has certain rights in the invention.