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Mapping virtual addresses to different physical addresses for value disambiguation for thread memory access requests

United States Patent

September 9, 2014
View the Complete Patent at the US Patent & Trademark Office
A multiprocessor system includes nodes. Each node includes a data path that includes a core, a TLB, and a first level cache implementing disambiguation. The system also includes at least one second level cache and a main memory. For thread memory access requests, the core uses an address associated with an instruction format of the core. The first level cache uses an address format related to the size of the main memory plus an offset corresponding to hardware thread meta data. The second level cache uses a physical main memory address plus software thread meta data to store the memory access request. The second level cache accesses the main memory using the physical address with neither the offset nor the thread meta data after resolving speculation. In short, this system includes mapping of a virtual address to a different physical addresses for value disambiguation for different threads.
Gala; Alan (Mount Kisco, NY), Ohmacht; Martin (Yorktown Heights, NY)
International Business Machines Corporation (Armonk, NY)
12/ 984,329
January 4, 2011
GOVERNMENT CONTRACT This invention was made with Government support under Contract No.: B554331 awarded by Department of Energy. The Government has certain rights in this invention.