There are disclosed herein various implementations of a transistor having a segmented gate region. Such a transistor may include at least one segmentation dielectric segment and two or more gate dielectric segments. The segmentation dielectric segment or segments are thicker than the gate dielectric segments, and is/are situated between the gate dielectric segments. The segmentation dielectric segment or segments cause an increase in the effective gate length so as to improve resistance to punch-through breakdown between a drain electrode and a source electrode of the transistor when the transistor is off.
STATEMENT OF GOVERNMENT INTEREST
This invention was made with Government support under Contract No. DE-AR0000016 awarded by Advanced Research Projects Agency-Energy (ARPA-E). The Government has certain rights in this invention.