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Heap/stack guard pages using a wakeup unit

United States Patent

April 29, 2014
View the Complete Patent at the US Patent & Trademark Office
A method and system for providing a memory access check on a processor including the steps of detecting accesses to a memory device including level-1 cache using a wakeup unit. The method includes invalidating level-1 cache ranges corresponding to a guard page, and configuring a plurality of wakeup address compare (WAC) registers to allow access to selected WAC registers. The method selects one of the plurality of WAC registers, and sets up a WAC register related to the guard page. The method configures the wakeup unit to interrupt on access of the selected WAC register. The method detects access of the memory device using the wakeup unit when a guard page is violated. The method generates an interrupt to the core using the wakeup unit, and determines the source of the interrupt. The method detects the activated WAC registers assigned to the violated guard page, and initiates a response.
Gooding; Thomas M. (Yorktown Heights, NY), Satterfield; David L. (Yorktown Heights, NY), Steinmacher-Burow; Burkhard (Yorktown Heights, NY)
International Business Machines Corporation (Armonk, NY)
12/ 696,817
January 29, 2010
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OF DEVELOPMENT This invention was made with Government support under Contract No.: B554331 awarded by the Department of Energy. The Government has certain rights in this invention.