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United States Patent

November 18, 2014
View the Complete Patent at the US Patent & Trademark Office
A system, method and computer program product for performing various store-operate instructions in a parallel computing environment that includes a plurality of processors and at least one cache memory device. A queue in the system receives, from a processor, a store-operate instruction that specifies under which condition a cache coherence operation is to be invoked. A hardware unit in the system runs the received store-operate instruction. The hardware unit evaluates whether a result of the running the received store-operate instruction satisfies the condition. The hardware unit invokes a cache coherence operation on a cache memory address associated with the received store-operate instruction if the result satisfies the condition. Otherwise, the hardware unit does not invoke the cache coherence operation on the cache memory device.
Chen; Dong (Croton-on-Hudson, NY), Heidelberger; Philip (Cortlandt Manor, NY), Kumar; Sameer (White Plains, NY), Ohmacht; Martin (Yorktown Heights, NY), Steinmacher-Burow; Burkhard (Esslingen, DE)
International Business Machines Corporation (Armonk, NY)
12/ 986,652
January 7, 2011
GOVERNMENT CONTRACT This invention was Government supported under Contract No. B554331 awarded by the Department of Energy. The Government has certain rights in this invention.