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Multiprocessor switch with selective pairing

United States Patent

March 11, 2014
View the Complete Patent at the US Patent & Trademark Office
System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory "nest" (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switch or a bus.
Gara; Alan (Mount Kisco, NY), Gschwind; Michael K. (Chappaqua, NY), Salapura; Valentina (Mount Kisco, NY)
International Business Machines Corporation (Armonk, NY)
13/ 027,882
February 15, 2011
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT The U.S. Government has a paid-up license in this invention and the right in limited circumstances to require the patent owner to license others on reasonable terms as provided for by the terms of Contract. No. B554331 awarded by the United States Department of Energy.