A technique for directly sharing physical memory between processes executing on processor cores is described. The technique includes loading a plurality of processes into the physical memory for execution on a corresponding plurality of processor cores sharing the physical memory. An address space is mapped to each of the processes by populating a first entry in a top level virtual address table for each of the processes. The address space of each of the processes is cross-mapped into each of the processes by populating one or more subsequent entries of the top level virtual address table with the first entry in the top level virtual address table from other processes.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH
This invention was developed with Government support under Contract No. DE-AC04-94AL850(X) between Sandia Corporation and the U.S. Department of Energy. The U.S. Government has certain rights in this invention.