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Efficiency of static core turn-off in a system-on-a-chip with variation

United States Patent

8,571,847
October 29, 2013
View the Complete Patent at the US Patent & Trademark Office
A processor-implemented method for improving efficiency of a static core turn-off in a multi-core processor with variation, the method comprising: conducting via a simulation a turn-off analysis of the multi-core processor at the multi-core processor's design stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's design stage includes a first output corresponding to a first multi-core processor core to turn off; conducting a turn-off analysis of the multi-core processor at the multi-core processor's testing stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's testing stage includes a second output corresponding to a second multi-core processor core to turn off; comparing the first output and the second output to determine if the first output is referring to the same core to turn off as the second output; outputting a third output corresponding to the first multi-core processor core if the first output and the second output are both referring to the same core to turn off.
Cher; Chen-Yong (Port Chester, NY), Coteus; Paul W. (Yorktown Heights, NY), Gara; Alan (Mount Kisco, NY), Kursun; Eren (Ossining, NY), Paulsen; David P. (Dodge Center, MN), Schuelke; Brian A. (Rochester, MN), Sheets, II; John E. (Zumbrota, MN), Tian; Shurong (Mount Kisco, NY)
International Business Machines Corporation (Armonk, NY)
12/ 727,984
20110172984
March 19, 2010
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT The present disclosure was made with the U.S. Government support under Contract No.: B554331 awarded by the U.S. Department of Energy. The U.S. Government has certain rights in this disclosure.