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Matrix multiplication operations with data pre-conditioning in a high performance computing architecture

United States Patent

8,577,950
November 5, 2013
View the Complete Patent at the US Patent & Trademark Office
Mechanisms for performing matrix multiplication operations with data pre-conditioning in a high performance computing architecture are provided. A vector load operation is performed to load a first vector operand of the matrix multiplication operation to a first target vector register. A load and splat operation is performed to load an element of a second vector operand and replicating the element to each of a plurality of elements of a second target vector register. A multiply add operation is performed on elements of the first target vector register and elements of the second target vector register to generate a partial product of the matrix multiplication operation. The partial product of the matrix multiplication operation is accumulated with other partial products of the matrix multiplication operation.
Eichenberger; Alexandre E. (Chappaqua, NY), Gschwind; Michael K. (Chappaqua, NY), Gunnels; John A. (Yorktown Heights, NY)
International Business Machines Corporation (Armonk, NY)
12/ 542,255
20110040821
August 17, 2009
GOVERNMENT RIGHTS This invention was made with United States Government support under Contract No. B554331 awarded by the Department of Energy. THE GOVERNMENT HAS CERTAIN RIGHTS IN THIS INVENTION.