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Growth of coincident site lattice matched semiconductor layers and devices on crystalline substrates

United States Patent

August 13, 2013
View the Complete Patent at the US Patent & Trademark Office
National Renewable Energy Laboratory - Visit the NREL Technology Transfer Website
Techniques for Growth of Lattice-Matched Semiconductor Layers
Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a substrate having a crystalline surface with a known lattice parameter (a). The method further includes growing a crystalline semiconductor layer on the crystalline substrate surface by coincident site lattice matched epitaxy, without any buffer layer between the crystalline semiconductor layer and the crystalline surface of the substrate. The crystalline semiconductor layer will be prepared to have a lattice parameter (a') that is related to the substrate lattice parameter (a). The lattice parameter (a') maybe related to the lattice parameter (a) by a scaling factor derived from a geometric relationship between the respective crystal lattices.
Norman; Andrew G. (Evergreen, CO), Ptak; Aaron J. (Littleton, CO)
Alliance for Sustainable Energy, LLC (Golden, CO)
12/ 643,127
December 21, 2009
CONTRACTUAL ORIGIN The United States Government has rights in this invention under Contract No. DE-AC36-08GO28308 between the United States Department of Energy and the Alliance for Sustainable Energy, LLC, the manager and operator of the National Renewable Energy Laboratory.