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Ordering of guarded and unguarded stores for no-sync I/O

United States Patent

8,473,683
June 25, 2013
View the Complete Patent at the US Patent & Trademark Office
A parallel computing system processes at least one store instruction. A first processor core issues a store instruction. A first queue, associated with the first processor core, stores the store instruction. A second queue, associated with a first local cache memory device of the first processor core, stores the store instruction. The first processor core updates first data in the first local cache memory device according to the store instruction. The third queue, associated with at least one shared cache memory device, stores the store instruction. The first processor core invalidates second data, associated with the store instruction, in the at least one shared cache memory. The first processor core invalidates third data, associated with the store instruction, in other local cache memory devices of other processor cores. The first processor core flushing only the first queue.
Gara; Alan (Mount Kisco, NY), Ohmacht; Martin (Yorktown Heights, NY)
International Business Machines Corporation (Armonk, NY)
12/ 986,349
20110173394
January 7, 2011
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OF DEVELOPMENT The U.S. Government has a paid-up license in this invention and the right in limited circumstances to require the patent owner to license others on reasonable terms as provided for by the terms of Contract. No. B554331 awarded by the Department of Energy.