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Combined group ECC protection and subgroup parity protection

United States Patent

June 18, 2013
View the Complete Patent at the US Patent & Trademark Office
A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group of n bits with P produces m redundant error correction code (ECC) protection bits, and two columns of P provide parity protection for subgroups of said given group of n bits. In the preferred embodiment of the invention, the matrix P is constructed by generating permutations of m bit wide vectors with three or more, but an odd number of, elements with value one and the other elements with value zero; and assigning said vectors to rows of the matrix P.
Gara; Alan G. (Mount Kisco, NY), Chen; Dong (Croton on Hudson, NY), Heidelberger; Philip (Cortlandt Manor, NY), Ohmacht; Martin (Yorktown Heights, NY)
International Business Machines Corporation (Armonk, NY)
11/ 768,527
June 26, 2007
GOVERNMENT RIGHTS This invention was made with Government support under Contract No.: B554331, awarded by Department of Energy. The Government has certain rights to this invention.