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Insertion of operation-and-indicate instructions for optimized SIMD code

United States Patent

June 4, 2013
View the Complete Patent at the US Patent & Trademark Office
Mechanisms are provided for inserting indicated instructions for tracking and indicating exceptions in the execution of vectorized code. A portion of first code is received for compilation. The portion of first code is analyzed to identify non-speculative instructions performing designated non-speculative operations in the first code that are candidates for replacement by replacement operation-and-indicate instructions that perform the designated non-speculative operations and further perform an indication operation for indicating any exception conditions corresponding to special exception values present in vector register inputs to the replacement operation-and-indicate instructions. The replacement is performed and second code is generated based on the replacement of the at least one non-speculative instruction. The data processing system executing the compiled code is configured to store special exception values in vector output registers, in response to a speculative instruction generating an exception condition, without initiating exception handling.
Eichenberger; Alexandre E. (Chappaqua, NY), Gara; Alan (Mount Kisco, NY), Gschwind; Michael K. (Chappaqua, NY)
International Business Machines Corporation (Armonk, NY)
12/ 543,628
August 19, 2009
This invention was made with United States Government support under Contract No. B554331 awarded by the Department of Energy. THE GOVERNMENT HAS CERTAIN RIGHTS IN THIS INVENTION.