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Pausing and activating thread state upon pin assertion by external logic monitoring polling loop exit time condition

United States Patent

May 21, 2013
View the Complete Patent at the US Patent & Trademark Office
A system and method for enhancing performance of a computer which includes a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processer. The processor processes instructions from the program. A wait state in the processor waits for receiving specified data. A thread in the processor has a pause state wherein the processor waits for specified data. A pin in the processor initiates a return to an active state from the pause state for the thread. A logic circuit is external to the processor, and the logic circuit is configured to detect a specified condition. The pin initiates a return to the active state of the thread when the specified condition is detected using the logic circuit.
Chen; Dong (Yorktown Heights, NY), Giampapa; Mark (Yorktown Heights, NY), Heidelberger; Philip (Yorktown Heights, NY), Ohmacht; Martin (Yorktown Heights, NY), Satterfield; David L. (Tewksbury, MA), Steinmacher-Burow; Burkhard (Boeblingen, DE), Sugavanam; Krishnan (Yorktown Heights, NY)
International Business Machines Corporation (Armonk, NY)
12/ 684,860
January 8, 2010
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OF DEVELOPMENT This invention was made with Government support under Contract No.: B554331 awarded by the Department of Energy. The Government has certain rights in this invention.