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Generating and executing programs for a floating point single instruction multiple data instruction set architecture

United States Patent

8,423,983
April 16, 2013
View the Complete Patent at the US Patent & Trademark Office
Mechanisms for generating and executing programs for a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA) are provided. A computer program product comprising a computer recordable medium having a computer readable program recorded thereon is provided. The computer readable program, when executed on a computing device, causes the computing device to receive one or more instructions and execute the one or more instructions using logic in an execution unit of the computing device. The logic implements a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA), based on data stored in a vector register file of the computing device. The vector register file is configured to store both scalar and floating point values as vectors having a plurality of vector elements.
Gschwind; Michael K. (Chappaqua, NY)
International Business Machines Corporation (Armonk, NY)
12/ 250,581
20100095098
October 14, 2008
GOVERNMENT RIGHTS This invention was made with United States Government support under Contract No. B554331 awarded by the Department of Energy. THE GOVERNMENT HAS CERTAIN RIGHTS IN THIS INVENTION.