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Global synchronization of parallel processors using clock pulse width modulation

United States Patent

April 2, 2013
View the Complete Patent at the US Patent & Trademark Office
A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.
Chen; Dong (Yorktown Heights, NY), Ellavsky; Matthew R. (Rochester, MN), Franke; Ross L. (Rochester, MN), Gara; Alan (Yorktown Heights, NY), Gooding; Thomas M. (Rochester, MN), Haring; Rudolf A. (Yorktown Heights, NY), Jeanson; Mark J. (Rochester, MN), Kopcsay; Gerard V. (Yorktown Heights, NY), Liebsch; Thomas A. (Sious Falls, SD), Littrell; Daniel (Carmel, NY), Ohmacht; Martin (Yorktown Heights, NY), Reed; Don D. (Rochester, MN), Schenck; Brandon E. (Rochester, MN), Swetz; Richard A. (Mahopac, NY)
International Business Machines Corporation (Armonk, NY)
12/ 696,764
January 29, 2010
STATEMENT OF GOVERNMENT RIGHTS This invention was made with Government support under Contract No. B554331 awarded by the Department of Energy. The Government has certain rights in the invention.