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Simplifying and speeding the management of intra-node cache coherence

United States Patent

April 17, 2012
View the Complete Patent at the US Patent & Trademark Office
Lawrence Livermore National Laboratory - Visit the Industrial Partnerships Office Website
A method and apparatus for managing coherence between two processors of a two processor node of a multi-processor computer system. Generally the present invention relates to a software algorithm that simplifies and significantly speeds the management of cache coherence in a message passing parallel computer, and to hardware apparatus that assists this cache coherence algorithm. The software algorithm uses the opening and closing of put/get windows to coordinate the activated required to achieve cache coherence. The hardware apparatus may be an extension to the hardware address decode, that creates, in the physical memory address space of the node, an area of virtual memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements.
Blumrich; Matthias A. (Ridgefield, CT), Chen; Dong (Croton on Hudson, NY), Coteus; Paul W. (Yorktown Heights, NY), Gara; Alan G. (Mount Kisco, NY), Giampapa; Mark E. (Irvington, NY), Heidelberger; Phillip (Cortlandt Manor, NY), Hoenicke; Dirk (Ossining, NY), Ohmacht; Martin (Yorktown Heights, NY)
International Business Machines Corporation (Armonk, NY)
12/ 953,770
November 24, 2010
This invention was made with Government support under subcontract number B517552 under prime contract number W-7405-ENG-48 awarded by the Department of Energy. The Government has certain rights in this invention.