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Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan

United States Patent

March 20, 2012
View the Complete Patent at the US Patent & Trademark Office
An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software.
Bellofatto; Ralph E. (Ridgefield, CT), Ellavsky; Matthew R. (Rochester, MN), Gara; Alan G. (Mount Kisco, NY), Giampapa; Mark E. (Irvington, NY), Gooding; Thomas M. (Rochester, MN), Haring; Rudolf A. (Cortlandt Manor, NY), Hehenberger; Lance G. (Leander, TX), Ohmacht; Martin (Yorktown Heights, NY)
International Business Machines Corporation (Armonk, NY)
11/ 768,791
June 26, 2007
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OF DEVELOPMENT The U.S. Government has a paid-up license in this invention and the right in limited circumstances to require the patent owner to license others on reasonable terms as provided for by the terms of Contract. No. B554331 awarded by the Department of Energy.