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Error correcting code with chip kill capability and power saving enhancement

United States Patent

August 30, 2011
View the Complete Patent at the US Patent & Trademark Office
A method and system are disclosed for detecting memory chip failure in a computer memory system. The method comprises the steps of accessing user data from a set of user data chips, and testing the user data for errors using data from a set of system data chips. This testing is done by generating a sequence of check symbols from the user data, grouping the user data into a sequence of data symbols, and computing a specified sequence of syndromes. If all the syndromes are zero, the user data has no errors. If one of the syndromes is non-zero, then a set of discriminator expressions are computed, and used to determine whether a single or double symbol error has occurred. In the preferred embodiment, less than two full system data chips are used for testing and correcting the user data.
Gara; Alan G. (Mount Kisco, NY), Chen; Dong (Croton On Husdon, NY), Coteus; Paul W. (Yorktown Heights, NY), Flynn; William T. (Rochester, MN), Marcella; James A. (Rochester, MN), Takken; Todd (Brewster, NY), Trager; Barry M. (Yorktown Heights, NY), Winograd; Shmuel (Scarsdale, NY)
International Business Machines Corporation (Armonk, NY)
11/ 768,559
June 26, 2007
GOVERNMENT RIGHTS This invention was made with Government support under Contract No.: B554331, awarded by Department of Energy. The Government has certain rights to this invention.