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Floating point only SIMD instruction set architecture including compare, select, Boolean, and alignment operations

United States Patent

7,900,025
March 1, 2011
View the Complete Patent at the US Patent & Trademark Office
Mechanisms for implementing a floating point only single instruction multiple data instruction set architecture are provided. A processor is provided that comprises an issue unit, an execution unit coupled to the issue unit, and a vector register file coupled to the execution unit. The execution unit has logic that implements a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA). The floating point vector registers of the vector register file store both scalar and floating point values as vectors having a plurality of vector elements. The processor may be part of a data processing system.
Gschwind; Michael K. (Chappaqua, NY)
International Business Machines Corporation (Armonk, NY)
12/ 250,575
20100095097
October 14, 2008
GOVERNMENT RIGHTS This invention was made with United States Government support under Contract No. B554331 awarded by the Department of Energy. THE GOVERNMENT HAS CERTAIN RIGHTS IN THIS INVENTION.