Skip to Content
Find More Like This
Return to Search

Static power reduction for midpoint-terminated busses

United States Patent

January 18, 2011
View the Complete Patent at the US Patent & Trademark Office
A memory system is disclosed which is comprised of a memory controller and addressable memory devices such as DRAMs. The invention provides a programmable register to control the high vs. low drive state of each bit of a memory system address and control bus during periods of bus inactivity. In this way, termination voltage supply current can be minimized, while permitting selected bus bits to be driven to a required state. This minimizes termination power dissipation while not affecting memory system performance. The technique can be extended to work for other high-speed busses as well.
Coteus; Paul W. (Yorktown Heights, NY), Takken; Todd (Brewster, NY)
International Business Machines Corporation (Armonk, NY)
11/ 768,552
June 26, 2007
GOVERNMENT RIGHTS This invention was made with Government support under Contract No.: B 554331, awarded by Department of Energy. The Government has certain rights to this invention.