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Low latency, high bandwidth data communications between compute nodes in a parallel computer

United States Patent

7,827,024
November 2, 2010
View the Complete Patent at the US Patent & Trademark Office
Methods, parallel computers, and computer program products are disclosed for low latency, high bandwidth data communications between compute nodes in a parallel computer. Embodiments include receiving, by an origin direct memory access (`DMA`) engine of an origin compute node, data for transfer to a target compute node; sending, by the origin DMA engine of the origin compute node to a target DMA engine on the target compute node, a request to send (`RTS`) message; transferring, by the origin DMA engine, a predetermined portion of the data to the target compute node using memory FIFO operation; determining, by the origin DMA engine whether an acknowledgement of the RTS message has been received from the target DMA engine; if the an acknowledgement of the RTS message has not been received, transferring, by the origin DMA engine, another predetermined portion of the data to the target compute node using a memory FIFO operation; and if the acknowledgement of the RTS message has been received by the origin DMA engine, transferring, by the origin DMA engine, any remaining portion of the data to the target compute node using a direct put operation.
Archer; Charles J. (Rochester, MN), Blocksome; Michael A. (Rochester, MN), Ratterman; Joseph D. (Rochester, MN), Smith; Brian E. (Rochester, MN)
International Business Machines Corporation (Armonk, NY)
11/ 746,333
20080281997
May 9, 2007
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT This invention was made with Government support under Contract No. B554331 awarded by the Department of Energy. The Government has certain rights in this invention.