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Chaining direct memory access data transfer operations for compute nodes in a parallel computer

United States Patent

7,805,546
September 28, 2010
View the Complete Patent at the US Patent & Trademark Office
Methods, systems, and products are disclosed for chaining DMA data transfer operations for compute nodes in a parallel computer that include: receiving, by an origin DMA engine on an origin node in an origin injection FIFO buffer for the origin DMA engine, a RGET data descriptor specifying a DMA transfer operation data descriptor on the origin node and a second RGET data descriptor on the origin node, the second RGET data descriptor specifying a target RGET data descriptor on the target node, the target RGET data descriptor specifying an additional DMA transfer operation data descriptor on the origin node; creating, by the origin DMA engine, an RGET packet in dependence upon the RGET data descriptor, the RGET packet containing the DMA transfer operation data descriptor and the second RGET data descriptor; and transferring, by the origin DMA engine to a target DMA engine on the target node, the RGET packet.
Archer; Charles J. (Rochester, MN), Blocksome; Michael A. (Rochester, MN)
International Business Machines Corporation (Armonk, NY)
11/ 829,325
20090031055
July 27, 2007
RESEARCH OR DEVELOPMENT This invention was made with Government support under Contract No. B554331 awarded by the Department of Energy. The Government has certain rights in this invention.