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Printable semiconductor structures and related methods of making and assembling

United States Patent

September 21, 2010
View the Complete Patent at the US Patent & Trademark Office
The present invention provides a high yield pathway for the fabrication, transfer and assembly of high quality printable semiconductor elements having selected physical dimensions, shapes, compositions and spatial orientations. The compositions and methods of the present invention provide high precision registered transfer and integration of arrays of microsized and/or nanosized semiconductor structures onto substrates, including large area substrates and/or flexible substrates. In addition, the present invention provides methods of making printable semiconductor elements from low cost bulk materials, such as bulk silicon wafers, and smart-materials processing strategies that enable a versatile and commercially attractive printing-based fabrication platform for making a broad range of functional semiconductor devices.
Nuzzo; Ralph G. (Champaign, IL), Rogers; John A. (Champaign, IL), Menard; Etienne (Urbana, IL), Lee; Keon Jae (Tokyo, JP), Khang; Dahl-Young (Urbana, IL), Sun; Yugang (Westmont, IL), Meitl; Matthew (Champaign, IL), Zhu; Zhengtao (Rapid City, SD), Ko; Heung Cho (Urbana, IL), Mack; Shawn (Goleta, CA)
The Board of Trustees of the University of Illinois (Urbana, IL)
11/ 421,654
June 1, 2006
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT This invention was made, at least in part, with United States governmental support awarded by Department of Energy under Grant No. DEFG02-91ER45439 and the Defense Advanced Projects Agency under Contract F8650-04-C-710. The United States Government has certain rights in this invention.