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System and method for programmable bank selection for banked memory subsystems

United States Patent

September 7, 2010
View the Complete Patent at the US Patent & Trademark Office
A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each of the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.
Blumrich; Matthias A. (Ridgefield, CT), Chen; Dong (Croton on Hudson, NY), Gara; Alan G. (Mount Kisco, NY), Giampapa; Mark E. (Irvington, NY), Hoenicke; Dirk (Seebruck-Seeon, DE), Ohmacht; Martin (Yorktown Heights, NY), Salapura; Valentina (Chappaqua, NY), Sugavanam; Krishnan (Mahopac, NY)
International Business Machines Corporation (Armonk, NY)
11/ 768,805
June 26, 2007
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OF DEVELOPMENT The U.S. Government has a paid-up license in this invention and the right in limited circumstances to require the patent owner to license others on reasonable terms as provided for by the terms of Contract. No. B554331 awarded by the Department of Energy.