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Allocating application to group of consecutive processors in fault-tolerant deadlock-free routing path defined by routers obeying same rules for path selection

United States Patent

July 21, 2009
View the Complete Patent at the US Patent & Trademark Office
Sandia National Laboratories - Visit the Intellectual Property Management and Licensing Website
In a multiple processor computing apparatus, directional routing restrictions and a logical channel construct permit fault tolerant, deadlock-free routing. Processor allocation can be performed by creating a linear ordering of the processors based on routing rules used for routing communications between the processors. The linear ordering can assume a loop configuration, and bin-packing is applied to this loop configuration. The interconnection of the processors can be conceptualized as a generally rectangular 3-dimensional grid, and the MC allocation algorithm is applied with respect to the 3-dimensional grid.
Leung; Vitus J. (Albuquerque, NM), Phillips; Cynthia A. (Albuquerque, NM), Bender; Michael A. (East Northport, NY), Bunde; David P. (Urbana, IL)
Sandia Corporation (Albuquerque, NM)
11/ 110,206
April 19, 2005
This invention was developed under Contract DE-AC04-94AL8500 between Sandia Corporation and the U.S. Department of Energy. The U.S. Government has certain rights in this invention.